Tutorial Overview
The Virtex-5 FPGA is particularly useful in Ethernet applications because it contains embedded Tri-mode 10/100/1000 Mbps Ethernet MACs. If you have done Ethernet designs before, you will know that Xilinx’s “soft” Ethernet MAC IP cores are not free and designing one yourself would be quite an undertaking. In this tutorial, we will generate an embedded Tri-mode Ethernet MAC IP wrapper using the Xilinx CORE Generator version 10.1.
Requirements
Before following this tutorial, you will need to do the following:
- You will need CORE Generator version 10.1.03 installed for this tutorial.
Generate the Tri-mode Ethernet MAC IP Wrapper
Follow these instructions for generating the Ethernet MAC IP wrapper.
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From the “Start” menu, open Xilinx CORE Generator.
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Select “File->New Project”.
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Click “Browse” and select an appropriate location for the Coregen project. Select the folder where you normally place your projects, for example “C:\ML505\Projects”, and create a sub-folder called “TEMACCore”. Open this folder and click “OK”.
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You will be asked for the specifications of the FPGA you are using. All the cores you generate under this CORE Generator project file will be customized for the FPGA you specify here. Under the “Part” tab, select these options: Family “Virtex5”, Device “xc5vlx50t”, Package “ff1136”, Speed grade “-1”. Click “OK”. Note: If you are not using the ML505 board, these specifications may not apply to you. You will have to enter the details corresponding to the specific FPGA that you are using.
Under the “Generation” tab, you can specify how you want your IP cores to be generated. Be sure that “VHDL” output is selected as shown below. 
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When you have created your CORE Generator project, click on the “View by Function” tab to get a list of cores that you are able to generate.
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Open “Communication & Networking->Ethernet” and double-click on “Virtex-5 Embedded Tri-mode Ethernet MAC Wrapper”.
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A dialog box should open to allow you to select the features of the Ethernet MAC Core you want. For each page, enter the settings as shown below.
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Click “Finish”. Your Ethernet MAC wrapper will be generated and CORE Generator will display a list of all the generated files. Close this window, and close CORE Generator.
Examine the Generated Files
We will now examine the generated files and explain their purpose and utility. Open “Windows Explorer” and browse to the Coregen folder that we just created. We should see a list of files as shown below:
We can see that CORE Generator has placed some files in the coregen project folder, and it has also created a folder specifically for the Ethernet MAC wrapper called v5_emac_v1_5. We will discuss the files that you will find most useful.
- **Instantiation Template File (v5_emac_v1_5.vho)**The instantiation template provides a template for declaring the Ethernet MAC component and instantiating it. If you are already familiar with the Ethernet MAC core, you could use this template by copying and pasting it to your design and making the necessary connections. If it is your first time using the core, you might prefer to use the examples provided in the
v5_emac_v1_5folder.
- **Ethernet MAC Core Datasheet (doc\v5_emac_ds550.pdf)**The datasheet provides the technical specifications for the Ethernet MAC core such as the total resources that it occupies and a short description of its parameters. It also contains an overview of the provided example.
- **Ethernet MAC Core Getting Started Guide (doc\v5_emac_gsg340.pdf)**The getting started guide is probably the most useful document for people new to the Ethernet MAC core. It provides an introduction to the core and gives a detailed description of the example that is generated with the core. It also contains instructions on how to simulate/implement the example.
- Example Design folderIn the
example_designfolder you will find the source code for the example described in the Getting Started Guide and also the wrapper for the Ethernet MAC core. Remember, you will not find VHDL source for the Ethernet MAC, because it is an embedded hardware device, not a “soft” core. In this folder you will also find the .ucf constraints file for use with the example. The provided example can be implemented in ISE and it includes an address swap module that loops all received Ethernet packets back to the source after swapping the MAC source/destination addresses in the packet. The example design can be tested by connecting the ML505 board to the Ethernet socket of your PC and using the open source Wireshark software to monitor your Ethernet traffic. Read the Getting Started Guide for more details. - Simulation folderThe “simulation” folder contains testbenches for simulating the Ethernet MAC core example.
The Coregen folder for this tutorial can be downloaded in a compressed ZIP file. Please select the file corresponding to your board, right-click on it and select “Save Link As”.
Board
Virtex-5 Version
ZIP file
XC5VLX50T
XC5VSX50T
XC5VFX70T
XC5VLX110T