Introducing the Quad Gigabit Ethernet FMC
Posted on October 13, 2014
| Jeff Johnson
Here’s the next product in Opsero’s growing lineup of FPGA I/O cards: the Quad Gigabit Ethernet FMC. This low-pin-count FMC is loaded with four Marvell Gigabit Ethernet PHYs and enables FPGA networking applications on the ZedBoard and other LPC carriers. A demo design for the ZedBoard is available on Github at the link below and further demos will become available in the next few weeks:
https://github.com/fpgadeveloper/zedboard-qgige
Look out for more details including the technical specs, schematics and more on the soon to be launched product page.
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SERDES FMC first units
Posted on October 6, 2014
| Jeff Johnson
Here’s a peek at the first units of the SERDES FMCs, the first low pin-count FPGA Mezzanine Card to enable multi-gigabit transceivers on the ZedBoard and other FPGA boards that don’t have internal MGTs. The first board is designed for SFP modules for Ethernet and optical applications whereas the second board has SATA connectors for custom applications. Both boards are compliant to the VITA 57 standard.
Stay tuned for the performance results this week!
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PCBs for the SERDES FMC
Posted on September 25, 2014
| Jeff Johnson
Yesterday I received the bare PCBs for the SERDES SFP FMC, my new product that enables 2 multi-gigabit transceivers on the ZedBoard or other LPC FMC carriers that don’t have internal MGTs.
In the last couple of weeks I’ve been working hard on a demo design in Vivado which you can find on Github here:
https://github.com/fpgadeveloper/zedboard-serdes-sfp-fmc
So far all timing passes at the board’s top speed of 3.125Gbps (or 2.5Gbps with DC balanced encoding).
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A first look at a first product
Posted on September 5, 2014
| Jeff Johnson
After years designing products for other companies, I’ve finally designed something for my own company.
If you have a ZedBoard and you want to experiment with MGTs, now you can with my two new SERDES low-pin-count FMCs. Both boards use the DS32EL0421/DS32EL0124 serializer/deserializer devices from Texas Instruments to provide two external multi-gigabit transceivers from any standard FMC carrier regardless of whether the FPGA has internal MGTs or not. The external MGTs can transmit and receive data up to 2.
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Using the AXI DMA in Vivado
Posted on August 6, 2014
| Jeff Johnson
Update 2017-10-10: I’ve turned this tutorial into a video here for Vivado 2017.2. In a previous tutorial I went through how to use the AXI DMA Engine in EDK, now I’ll show you how to use the AXI DMA in Vivado. We’ll create the hardware design in Vivado, then write a software application in the Xilinx SDK and test it on the MicroZed board (source code is shared on Github for the MicroZed and the ZedBoard, see links at the bottom).
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Creating a custom IP block in Vivado
Posted on August 4, 2014
| Jeff Johnson
Update 2017-11-01: Here’s a newer tutorial on creating a custom IP with AXI-Streaming interfaces
Tutorial Overview In this tutorial we’ll create a custom AXI IP block in Vivado and modify its functionality by integrating custom VHDL code. We’ll be using the Zynq SoC and the MicroZed as a hardware platform. For simplicity, our custom IP will be a multiplier which our processor will be able to access through register reads and writes over an AXI bus.
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Version control for Vivado projects
Posted on August 1, 2014
| Jeff Johnson
Vivado generates a whole bunch of files when you create a project, and it’s not very clear on which are source files and which are generated files. The best approach is to consider them all to be generated files and to put none of them in version control. Instead, create a folder stucture for your sources that makes sense to you and use Tcl scripts to build the project and import the sources.
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Creating a Base System for the Zynq in Vivado
Posted on July 31, 2014
| Jeff Johnson
Tutorial Overview In the ISE/EDK tools, we’d use the Base System Builder to generate a base project for a particular hardware platform. Now with Vivado, the process is a little different but we have more control in how things are setup and we still benefit from some powerful automation features. In this tutorial we’ll create a base design for the Zynq in Vivado and we’ll use the MicroZed board as the hardware platform.
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Zynq and the trend towards ARM-FPGA architectures
Posted on June 16, 2014
| Jeff Johnson
Since the release of the Series 7 devices from Xilinx in 2011, one member of the family is clearly dominating the others in terms of popularity: the Zynq-7000 SoC. Did Xilinx put all their marketing efforts into the Zynq or is this proof of a new trend in FPGA technology?
To answer that question let me talk about why I think the Zynq SoC has been so popular.
The Zynq bridges a gap in the market for high-performance, calculation-intensive devices.
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Modifying a BSP in Xilinx SDK
Posted on May 28, 2014
| Jeff Johnson
If ever you need to modify the BSP code in your Xilinx SDK project, keep two things in mind:
Remember to re-build your application after the BSP has finished re-building. If you don’t re-build the software application, the .elf file will still contain the old BSP code and you wont see any change. Just re-save one of your application source files to get SDK to re-build your application. NEVER do a “clean” on the BSP after having modified it because Xilinx SDK deletes the BSP and re-builds them from the repository sources located in C:\Xilinx\14.
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