FPGA Developer

I just received the Zynq-7000 based ZC706 development board from a new client and I’m pretty excited to start working on it. This is the first time that I’ll be working on the Zynq FPGA, part of the latest series 7 devices from Xilinx, so over the next few days, I’ll be writing about my experiences while getting familiar with the board, the FPGA and version 14.5 of the Xilinx development tools. If I get time later, I might dive into the new Vivado Design Suite, promoted by Xilinx to be a “revolutionary IP-centric and system-centric design environment for dramatically faster integration and implementation” - we’ll see about that.

I was looking around for FPGA based PCIe boards when I came across something interesting from Nallatech. They’ve created two OpenCL compatible PCIe boards designed especially for the finance market. Named rather creatively “Nallatech 385” and “Nallatech 395”, they’re both based on the Stratix V from Altera which is the best of Altera’s high-end FPGAs. Both boards have a PCIe Gen3 x 8 lane host interface that should allow you to transfer data between the FPGA and the host machine at about 7.88 gigabytes per second (985MB/s per lane x 8). For connection to the market, the boards have SFP+ cages into which you can plug modules for 1Gb Ethernet, 10Gb Ethernet, SONET/SDH & OTN. The main differences between the boards seems to be the amount and speed of the on-board memory and the number of network interfaces.

I was looking around for FPGA based PCIe boards when I came across something interesting from Nallatech. They’ve created two OpenCL compatible PCIe boards designed especially for the finance market. Named rather creatively “Nallatech 385” and “Nallatech 395”, they’re both based on the Stratix V from Altera which is the best of Altera’s high-end FPGAs. Both boards have a PCIe Gen3 x 8 lane host interface that should allow you to transfer data between the FPGA and the host machine at about 7.88 gigabytes per second (985MB/s per lane x 8). For connection to the market, the boards have SFP+ cages into which you can plug modules for 1Gb Ethernet, 10Gb Ethernet, SONET/SDH & OTN. The main differences between the boards seems to be the amount and speed of the on-board memory and the number of network interfaces.

I’m now fully committed to consulting through my new company: Opsero Electronic Design.

I’m offering FPGA design services including:

• HDL Programming
• IP core design
• EDK/ISE project design
• Design modification
• Simulation
• Hardware verification
• Debugging
• Timing closure

I’m also offering electronic hardware design services including:

• System architecture design
• Analog, digital and mixed circuits
• Parts selection
• Schematic capture
• Verification through SPICE simulation
• SPICE model creation
• PCB layout

If you need a consultant for any of the above services, don’t hesitate to contact me through my company website.

I’ve left my full-time job to start a business in electronics consulting! It feels good to finally follow my dream.

I’m asking my readers for help in choosing a company name, please vote!

Update 9-7-2013: The voting is closed. Opsero wins by 2 votes! Thanks to everyone who voted!

Let’s say we want to be able to switch dynamically between two (or more) clocks. In the Virtex FPGAs we have a primitive which allows us to do just this, it’s called the BUFGCTRL. The BUFGCTRL is a global clock buffer (like BUFG) which has two clock inputs and a series of control inputs that allow you to select between the two clocks. The great thing about the BUFGCTRL is that it allows you to switch between clocks “glitch free”.

For the occasions that you find yourself with a netlist file and you don’t know where it came from or what version it is, etc. this post is about how you can interpret the netlist file (ie. convert it into something readable).

Today I found myself with two netlists and I needed to know if they were the same. Yes of course you can try comparing the two files with a program such as Beyond Compare, but if the netlists were compiled on separate dates, you will have trouble recognizing this from the raw binary data. The best thing to do in this case is to convert the netlists to EDIF files, a readable, text file version of the netlist. Another option is to convert the netlists into VHDL or Verilog code. Here is how you can do this:

Back in 2009 I did a presentation on why companies needed to be using FPGAs in their high frequency trading:

Why You Need FPGA In Your High-Frequency Trading Business

View more presentations from jeffjohnsonau

Now every man and his dog are trading with FPGAs and the edge is now blunt as a spoon. But rather than a time to walk away it’s time to change tactics. Here’s what you should be doing now:

Not long ago I discovered GitHub, the social coding website. Basically its a place where you can share your code and manage open source projects online. I think it’s mainly used by non-HDL programmers but the concept is not language specific so I figured it would be a good place to share FPGA designs. Gradually I will bring all the source code of all our tutorials onto GitHub so that people can more easily share it, modify it and contribute to it.

Here is a recent presentation I made on outsourcing FPGA design work.

Outsourcing FPGA Design: Pros and cons

View more presentations from jeffjohnsonau.