Nallatech Releases FPGA Boards for High Frequency Trading

Nallatech Releases FPGA Boards for High Frequency Trading

 Posted on June 30, 2013  |  Jeff Johnson

I was looking around for FPGA based PCIe boards when I came across something interesting from Nallatech. They’ve created two OpenCL compatible PCIe boards designed especially for the finance market. Named rather creatively “Nallatech 385” and “Nallatech 395”, they’re both based on the Stratix V from Altera which is the best of Altera’s high-end FPGAs. Both boards have a PCIe Gen3 x 8 lane host interface that should allow you to transfer data between the FPGA and the host machine at about 7. [Read More]

Opsero Electronic Design

 Posted on June 2, 2013  |  Jeff Johnson

I’m now fully committed to consulting through my new company: Opsero Electronic Design. I’m offering FPGA design services including: HDL Programming IP core design EDK/ISE project design Design modification Simulation Hardware verification Debugging Timing closure I’m also offering electronic hardware design services including: System architecture design Analog, digital and mixed circuits Parts selection Schematic capture Verification through SPICE simulation SPICE model creation PCB layout If you need a consultant for any of the above services, don’t hesitate to contact me through my company website. [Read More]

Doing my own thing

 Posted on April 23, 2013  |  Jeff Johnson

I’ve left my full-time job to start a business in electronics consulting! It feels good to finally follow my dream.

I’m asking my readers for help in choosing a company name, please vote!

Update 9-7-2013: The voting is closed. Opsero wins by 2 votes! Thanks to everyone who voted!

Code templates: Clock MUX

 Posted on September 13, 2011  |  Jeff Johnson

Let’s say we want to be able to switch dynamically between two (or more) clocks. In the Virtex FPGAs we have a primitive which allows us to do just this, it’s called the BUFGCTRL. The BUFGCTRL is a global clock buffer (like BUFG) which has two clock inputs and a series of control inputs that allow you to select between the two clocks. The great thing about the BUFGCTRL is that it allows you to switch between clocks “glitch free”. [Read More]

How to read an NGC netlist file

 Posted on August 17, 2011  |  Jeff Johnson

For the occasions that you find yourself with a netlist file and you don’t know where it came from or what version it is, etc. this post is about how you can interpret the netlist file (ie. convert it into something readable). Today I found myself with two netlists and I needed to know if they were the same. Yes of course you can try comparing the two files with a program such as Beyond Compare, but if the netlists were compiled on separate dates, you will have trouble recognizing this from the raw binary data. [Read More]

FPGAs in High Frequency Trading

 Posted on August 9, 2011  |  Jeff Johnson

Back in 2009 I did a presentation on why companies needed to be using FPGAs in their high frequency trading: Why You Need FPGA In Your High-Frequency Trading Business View more presentations from jeffjohnsonau Now every man and his dog are trading with FPGAs and the edge is now blunt as a spoon. But rather than a time to walk away it’s time to change tactics. Here’s what you should be doing now: [Read More]

FPGA Developer is now on GitHub!

 Posted on August 7, 2011  |  Jeff Johnson

Not long ago I discovered GitHub, the social coding website. Basically its a place where you can share your code and manage open source projects online. I think it’s mainly used by non-HDL programmers but the concept is not language specific so I figured it would be a good place to share FPGA designs. Gradually I will bring all the source code of all our tutorials onto GitHub so that people can more easily share it, modify it and contribute to it. [Read More]
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Bitcoin mining with FPGAs

 Posted on July 19, 2011  |  Jeff Johnson

Recently, what looks to be the first open source FPGA bitcoin miner was released on GitHub. The code is based on the Terasic DE2-115 development board featuring the Altera Cyclone IV, however the author says the design should be applicable to any other FPGA. Maybe we should make it work on a Xilinx FPGA? Here is what they say about its performance: Project is fully functional and allows mining of Bitcoins both in a Pool and Solo. [Read More]
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Code templates: Generate for loop

 Posted on July 19, 2011  |  Jeff Johnson

This is the first part of a series of posts I will write on various code structures and examples for HDL designs. Here I want to talk about the generate statement and particularly the for loop. Most programmers think of a for loop as being a code segment that is repeated during execution of the program. The generate for loop is similar in concept however the difference is that the code segment is repeated on compilation time. [Read More]
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