List and comparison of FPGA companies
Posted on July 15, 2011
| Jeff Johnson
With the top two FPGA companies taking up 89% of the FPGA market, you can be forgiven for thinking there was no one else out there. Xilinx and Altera have done a good job of defending the duopoly but a few companies are gradually winning market share by targeting specific applications and sub-markets. Here is a list of the top 5 FPGA companies by revenue.
Chart: FPGA Market Share by 2010 revenue in Millions of USDDescription: This chart compares the 2010 revenues of Xilinx, Altera, Lattice Semiconductor, Microsemi and QuickLogic companies.
[Read More]
JP Morgan applies FPGA to risk management
Posted on July 12, 2011
| Jeff Johnson
You might already know I’m interested in the application of FPGAs in the financial markets, a field that has been growing over the last few years. JP Morgan has been working on this over the last 3 years and its paying off.
JP Morgan supercomputer offers risk analysis in near real-time
Prior to the implementation, JP Morgan would take eight hours to do a complete risk run, and an hour to run a present value, on its entire book.
[Read More]
How to melt an FPGA
Posted on July 11, 2011
| Jeff Johnson
Recently I was asked this question by a reader: “Is it possible to make a design large enough to make the FPGA melt?”.
I don’t know why you would want to melt an FPGA, but the idea is interesting so its worth writing about. I’ve actually had people tell me rumors that if you made a design that utilized 90-100% of the resources in an FPGA that it would melt itself.
[Read More]
Clocks, resets and wild goose chases
Posted on July 8, 2011
| Jeff Johnson
There’s a problem that I believe costs design companies billions of dollars a year whether they’re in hardware, software or FPGA design. The problem is hard to control, difficult to monitor and impossible to predict. The problem is bad design practice. Some people call everything “bugs”, but I prefer to call this problem poor design. It is what happens when you do those late-nighters and you’re too tired to see all the loose-ends you’re leaving in your code, or when you don’t have time to test every use case because the product release is yesterday.
[Read More]
Using a TCL script to automatically generate netlists of an IP core
Posted on July 6, 2011
| Jeff Johnson
In a previous post I wrote about using SVN with HDL designs and how to do it most effectively. Here I want to write about having your peripheral cores automatically generate the netlists they use when the project is compiled, for example when you build the bitstream of an XPS project. Firstly I’ll give you an example where it would be useful.
Let’s say I have a peripheral that contains a FIFO.
[Read More]
Is Xilinx losing to the competition?
Posted on July 5, 2011
| Jeff Johnson
I recently read an interesting article on Xilinx’s position with respect to its competitors: Is Xilinx Good Enough for You? As someone who works mainly with Xilinx FPGAs, I find it important to know how they are faring competitively. If one day a competitor manages to blow Xilinx out of the water, I would like to have seen it coming.
The image below was taken from Google Trends and shows Google search results for Xilinx and Altera.
[Read More]
Read DIP switches from a Microblaze application
Posted on July 5, 2011
| Jeff Johnson
In the previous tutorial on using the SDK, we exported our base project from EDK to SDK and then we ran a simple software application that printed “Hello World” in the terminal window. In this tutorial, we will do something more useful than saying hello, instead we will illustrate the concept of communicating with a peripheral from C code running on the Microblaze. More specifically, we will read the DIP switch settings and display them on the terminal screen using printfs.
[Read More]
The Virtex-6 based ML605
Posted on July 1, 2011
| Jeff Johnson
Forget about the ML505. The ML605 just made it obsolete. Not because of the Virtex-6 or the 8-lane PCIe or the DDR3… You need the ML605 because it has two FMC expansion connectors, one high-pin count and one low-pin count. You could do practically anything with this board. Why do I like it? Because for once we have a board that lets you interface real data at a high throughput to a beast of an FPGA.
[Read More]
How to read an NCD file
Posted on June 30, 2011
| Jeff Johnson
Sometimes we end up with two versions of the same design, where one works and one doesn’t work. If the code is the same, typically the problem is in placement of your primitives. In this case we would like to compare the two designs at a to find out what exactly has changed in the placements.
This is where reading the NCD file (the Native Circuit Description file) can be useful.
[Read More]
Using SVN with HDL designs
Posted on June 29, 2011
| Jeff Johnson
Most companies involved in code design manage their sources using SVN. If you’re not doing it, you should be. There are a multitude of websites explaining the benefits of using SVN so I wont go there. This post is about the best way to use SVN for HDL designs.
HDL designs typically involve source files, netlist files and bitstreams. As in software design, the best way to use SVN is to commit source files only.
[Read More]