FPGA Developer

Sometimes we end up with two versions of the same design, where one works and one doesn’t work. If the code is the same, typically the problem is in placement of your primitives. In this case we would like to compare the two designs at a to find out what exactly has changed in the placements.

This is where reading the NCD file (the Native Circuit Description file) can be useful. The NCD file is the product of PAR and the file used by bitgen to generate the bitstream.

Most companies involved in code design manage their sources using SVN. If you’re not doing it, you should be. There are a multitude of websites explaining the benefits of using SVN so I wont go there. This post is about the best way to use SVN for HDL designs.

HDL designs typically involve source files, netlist files and bitstreams. As in software design, the best way to use SVN is to commit source files only. That means, don’t commit netlist files or bitstream files. Our challenge is to ensure that someone who loads our sources from SVN to a clean slate (let’s call him Jack) will be able to re-generate the netlists and bitstream files without a problem.

In the previous tutorial titled Creating a project using Base System Builder, we used the Embedded Development Kit (EDK) to create a hardware design composed of IP cores and a Microblaze soft processor. In this tutorial, we will complete the design by writing a software application to run on the Microblaze processor. In version 13.1, this is done using the Software Development Kit (SDK) and it is no longer “doable” in the EDK. To keep things simple, we’ll start off with a “hello world” application and then move onto one that will communicate with our peripherals. Specifically, we will read the DIP switch settings and display them on the terminal screen using printfs.

Why can’t I find my signals in Chipscope inserter?

Often you want to assign a constraint to a particular signal in your design, or you want be able to find a particular signal in Chipscope inserter. In both cases, the signal must be in the physical design database (ie. in the .NCD file - Native Circuit Description) which is generated by the mapper. Not all signal names in your HDL code will end up in the NCD, some of them will be absorbed into logic blocks and grouped into a different signal name. To ensure that a particular signal name ends up in the NCD, it’s important to use the keep signal constraint.

The diagram below shows the EDK window with an open project. The important areas are labelled with numbers 1 to 6.

1. Project Information

This area contains information about the project and contains two tabs: Project and IP Catalog.

1. The Project tab lists the project files and also some of the project settings such as target FPGA.
2. The IP catalog contains a list of the peripherals or IP cores that your project has access to. You will use this tab when you want to instantiate IP cores into your design. Get information about cores by right clicking on them and clicking “View PDF datasheet”.

2. Bus connectivity

This area shows the interconnections between your IP cores, your memory and the Microblaze processor(s). You’ll notice two types of bus: the Processor Local Bus (PLB) and the Local Memory Bus (LMB).

The other day I wasted hours trying to figure out why my peripheral wasn’t properly clocking Chipscope. Basically I had my peripheral generating a clock and data which I plugged directly into a Chipscope ILA peripheral. When I looked at the Chipscope data, it was sort of random but sort of looked right at the same time.

I eventually realized that in my MPD file for the peripheral, I had forgotten to specify that my clock output was in fact a “clock” output by using the SIGIS = CLK parameter.

If you’re a hardware developer, you know the problem:

• My product integrates the FPGA and ADC on the one compact PCB, but now my customers want a higher-speed ADC, or a DAC, or both. Now I have to take on the risk of designing a whole new board to satisfy that demand.
• I’m getting killed on repairs because the cost of my field-replacable-unit is too high. Having too many high-cost devices on the same board is just not economical.

If you’re an FPGA developer, you know the problem:

For some reason, the Base System Builder in EDK doesn’t support the XUPV5 board so when making an EDK project for the XUPV5 we have to select the ML505 board and modify the project settings later. If you have not yet created an EDK project, you should read the previous post Creating a project using the Base System Builder, and then continue from these instructions.

What am I learning here?

In this post we’ll look at using the Base System Builder in EDK version 13.1. Specifically you’ll learn:

1. How to create an EDK project with the Base System Builder
2. How to add a software application to an EDK project
3. How to implement and test your design

Requirements

You will need the following :

• One ML505/ML506/ML507 or XUPV5 board (or actually any board supported by Xilinx).
• Xilinx ISE Design Suite 13.1 (including EDK)

Create the Basic Project

Follow these steps to create the basic project:

Some of you will know that I ran some polls on the site over the last couple of months. Well I checked out the results and accordingly there will be some big changes on the site, the first of which is that I’ve moved to WordPress and given the site a fresh new look.

Thanks to all the people who responded to the polls, your input was very very appreciated! Here are the changes: