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FPGA Developer
A tech blog on FPGA design by Jeff Johnson
Code templates: Generate for loop
VHDL and Verilog examples of the generate for loop for replicating hardware structures
July 19, 20113 minutes
List and comparison of FPGA companies
A comparison of the top five FPGA companies by revenue and market share
July 15, 20113 minutes
JP Morgan applies FPGA to risk management
JP Morgan uses FPGAs to reduce risk analysis run time from eight hours to seconds
July 12, 20111 minute
How to melt an FPGA
Exploring whether a design can generate enough heat to melt an FPGA and what limits exist
July 11, 20112 minutes
Clocks, resets and wild goose chases
A debugging war story about how poor clock and reset practices lead to elusive FPGA bugs
July 8, 20115 minutes
Using a TCL script to automatically generate netlists of an IP core
How to use a Tcl script to auto-regenerate CoreGen netlists when building an XPS project
July 6, 20113 minutes
Is Xilinx losing to the competition?
Analyzing Xilinx's competitive position versus Altera using market trends and search data
July 5, 20111 minute
Read DIP switches from a Microblaze application
Tutorial on reading DIP switches and displaying their state using a Microblaze C application
July 5, 20115 minutes
The Virtex-6 based ML605
A look at the ML605 evaluation board and its FMC expansion connectors for high-throughput I/O
July 1, 20112 minutes
How to read an NCD file
How to convert and inspect NCD files using the XDL tool and FPGA Editor
June 30, 20114 minutes