Use iMPACT to Download a Bit File

 Posted on October 10, 2009  |  Jeff Johnson

Instructions If you want to download a bit file (.bit) to your FPGA without using ISE or EDK, you can use iMPACT directly from the command line. To start, you should copy your bit file to a known folder (eg. “C:MyFolder”) and rename it to download.bit if it isn’t already called that. Then you should create an iMPACT script file called download.cmd. The script file is just a text file that you can create with Wordpad and it must contain the following text: [Read More]

Aurora to Ethernet Bridge

 Posted on September 24, 2009  |  Jeff Johnson

Tutorial Overview In the last tutorial we implemented the embedded Tri-mode Ethernet MAC and tested it by looping back Ethernet packets and monitoring them with Wireshark. In this tutorial, we will again implement the EMAC but this time we will link it to an Aurora core, to implement an Aurora to Ethernet Bridge. With the bridge, we can link two PCs as shown in the diagram below. To connect the EMAC and Aurora cores we have to use two FIFOs to cross clock domains. [Read More]
aurora  mgt  rocketio  virtex-5 

Generating Clock Domain Crossing FIFOs

 Posted on September 23, 2009  |  Jeff Johnson

Tutorial Overview In some FPGA designs, it is necessary to interface two devices that operate in different clock domains. One solution to crossing from one clock domain to another is by using FIFOs with independent read and write clocks. In this tutorial, we will generate FIFOs with independent read and write clocks, and non-symmetric aspect ratios. This tutorial was written for the Aurora to Ethernet Bridge project in which we want to interface the Ethernet MAC to the Aurora core. [Read More]
aurora 

Tri-mode Ethernet MAC

 Posted on October 20, 2008  |  Jeff Johnson

Tutorial Overview The Virtex-5 Embedded Tri-mode Ethernet MAC is useful for designs requiring Ethernet connectivity. Fortunately, Xilinx has made it easy for us to start developing with the Ethernet MACs by providing several online examples and application notes. One of the examples can be obtained when you use CORE Generator to generate the Ethernet MAC wrapper. The generated example is a simple design that mirrors incoming Ethernet packets, swapping the source and destination MAC addresses. [Read More]

XUPV2P Board

 Posted on October 19, 2008  |  Jeff Johnson

Hardware Details The Xilinx University Program Virtex-II Pro (XUPV2P) Development System from Digilent is a development board for the Virtex-II Pro FPGA. It contains many useful hardware features including: Xilinx Virtex-II Pro XC2VP30 FPGA 10/100Mbps Ethernet PHY USB port Compact Flash card slot XSGA Video port Audio Codec SATA connectors (2 hosts, 1 target) PS/2 and RS-232 ports High and Low Speed expansion connectors  Virtex-II Pro FPGA Details [Read More]

Basic Coregen Tutorial

 Posted on October 18, 2008  |  Jeff Johnson

Tutorial Overview In this tutorial, we will generate a Multiplier IP core using the Xilinx CORE Generator version 10.1. What will you learn By following this tutorial, you will learn: How to generate an IP core using the CORE Generator What files are generated and how to use them  Requirements Before following this tutorial, you will need to do the following: Buy an ML505/ML506/ML507 or XUPV5 board if you don’t already have one. [Read More]

Create a Peripheral using the Peripheral Wizard

 Posted on October 18, 2008  |  Jeff Johnson

Tutorial Overview In this tutorial we will create a simple project that uses our own IP peripheral (instead of using the XPS General Purpose IO peripheral provided by Xilinx) to read from the DIP switches and write to the LEDs. The software application will display the DIP switch values on the LED outputs and also send the DIP switch values to the UART. Any custom logic (IP) that you design must connect to the PLB to communicate with the Microblaze processor. [Read More]
peripheral 

Create a Project Using the Base System Builder

 Posted on October 18, 2008  |  Jeff Johnson

Tutorial Overview In this example, we will develop a simple FPGA project using the Base System Builder that includes three peripherals: the RS232 UART and two GPIOs. One GPIO will be used for the DIP switches and the other for the LEDs. We will then use a C program to read data from the switches and write it to the LEDs. The result is that the LEDs will display the DIP switch settings. [Read More]

Generating the Aurora Core

 Posted on October 18, 2008  |  Jeff Johnson

Tutorial Overview In this tutorial, we will generate an Aurora IP core using the Xilinx CORE Generator version 10.1. The Aurora core can be used as a high-speed serial communications link for connecting multiple FPGAs or interfacing to other serial devices. Requirements To generate the Aurora core with CORE Generator, you will first need to register with Xilinx to obtain a license to use the Aurora core. It is a free and simple process that involves accepting a license agreement. [Read More]
aurora