Python for the Zynq and the PYNQ-Z1
Being a big fan of Python, for ages I’ve wanted to explore the possibilities of running Python on the Zynq. Thankfully Xilinx and Digilent saw the value in this too and they developed the PYNQ-Z1 and more importantly the PYNQ libraries for Python. The PYNQ-Z1 is basically a single board computer based on the Zynq-7020 device from Xilinx. So thats got a dual core ARM plus integrated FPGA or programmable logic.
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IntelliProp Demos NVMe Host Accelerator on FPGA Drive
Early this year IntelliProp released a demo video of their NVMe Host Accelerator IP core running on the Intel Arria 10 GX FPGA Development board. As you can see in the video, they are using Opsero’s FPGA Drive product with the PCIe slot connector to interface the NVMe SSD to the FPGA board. They measured an impressive performance of around 2300MBps sequential write speed and 3200MBps sequential read speed.PetaLinux for Artix-7 Arty Base Project
In the final part of the Arty base project tutorial, we build a PetaLinux project that’s tailored to our Arty base design. Then we boot PetaLinux on our hardware and verify that we have network connectivity by checking the Arty’s DHCP assigned IP address and then pinging it from a PC. Tools used I used the following setup to do this project: Vivado 2017.3 on a Windows 10 machine PetaLinux 2017.Artix-7 Arty Base Project
Here’s a base project for the Arty board based on the Artix-7 FPGA. The Arty is a nice little dev board because it’s low cost ($99 USD) but it’s still got enough power and connectivity to make it very useful. I really like the fact that the JTAG and UART are both accessed through the same USB connector, so I only need to connect one USB cable.Creating a custom AXI-Streaming IP in Vivado
The AXI-Streaming interface is important for designs that need to process a stream of data, such as samples coming from an ADC, or images coming from a camera. In this tutorial, we go through the steps to create a custom IP in Vivado with both a slave and master AXI-Streaming interface. The custom IP will be written in Verilog and it will simply buffer the incoming data at the slave interface and make it available at the master interface - in other words, it will be a FIFO.Quick look at the UltraZed-EG SoM
In this video I take a look at the features of the UltraZed-EG System-on-Module and the Zynq UltraScale+ MPSoC. As is typical for Avnet products, it’s a great deal with a price tag of only $485 USD, when the device alone (XCZU3EG-1SFVA625E) would cost you $354 USD. This SoM can’t be used as an SBC (single board computer), it needs a carrier card such as the UltraZed PCIe Carrier Card; this board will cost you $499 USD and has most of the hardware you need to exploit the Zynq UltraScale+ device to its full potential: Gigabit Ethernet, Display Port, PCIe, USB3 and SATA among others.
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