Xilinx just released a video presenting the next-generation of All Programmable devices and dev environments. It’s a quick look at where technology is going and particularly where FPGAs are going to make their mark.
Of particular interest to me were the images of a Virtex Ultrascale PCI Express board at 2:45 in the video. This board appears to have both the PCIe gold-finger edge connector and a PCIe saddle-mount socket connector, so it could be used as either the PCIe end-point or the root complex - or maybe both at the same time.
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Rick Merritt wrote an interesting article on EETimes titled Red Hat Drives FPGAs, ARM Servers. It seems that Red Hat and the major FPGA vendors are going to get together in March to work out a standard software interface for FPGA accelerator boards. The success of high-level synthesis tools in recent years has re-ignited interest in FPGA-based hardware accelerators, as development times on FPGA hardware has seen massive reductions thanks to OpenCL and Vivado HLS, among others.
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Very excited to be showing off my new Samsung SSD 950 in the M.2 form factor. This tiny solid-state drive has a PCI Express Gen3 x 4-lane interface for a more direct connection to the CPU which enables a much higher throughput than a SATA interface. According to Samsung:
It outperforms SATA SSDs by over 4.5 times in sequential read and by over 2.5 times in sequential write, delivering the speeds of 2,500 MB/s and 1,500 MB/s respectively.
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Since their invention, FPGAs have been burdened by a problem that has held them back from more widespread adoption: they’re too hard to program. Xilinx knows this, which is why they spent hundreds of millions of dollars developing the Vivado Design Suite and more importantly Vivado HLS (high-level synthesis) which enables high-performance hardware designs to be programmed in C/C++. Well a new company called QuickPlay has created their own solution to this problem.
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Tutorial Overview This tutorial is the follow-up to Using AXI Ethernet Subsystem and GMII-to-RGMII in a Multi-port Ethernet design. In this part of the tutorial we will generate the bitstream, export the hardware description to the SDK and then test the echo server application on our hardware. The echo server application runs on lwIP (light-weight IP), the open source TCP/IP stack for embedded systems. Our hardware platform is the Avnet ZedBoard combined with the Ethernet FMC.
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I recently got myself a PicoZed 7Z030 SoM (system-on-module) so that I could start developing more resource intensive applications for the Ethernet FMC, such as network tapping and network latency measurement. Why would I use a SoM for this? Checkout my comparison of Zynq SoMs to learn more about the benefits of SoMs in product development.
It’s worth mentioning this arrived the day after I ordered it. Here are some photos I took while unboxing:
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When designing a network tap on an FPGA, the logical place to start is the pass-through between two Ethernet ports. In this article, I’ll discuss a convenient way to connect two Ethernet ports at the PHY-MAC interface, which will form the basis of a network tap. The pass-through will be designed in Vivado for the ZedBoard combined with an Ethernet FMC. In future articles, I’ll discuss other aspects of an FPGA network tap design, including monitor ports, packet filtering, and opportunities for hardware acceleration in the FPGA.
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Tutorial Overview In this two-part tutorial, we’re going to create a multi-port Ethernet design in Vivado 2015.4 using both the GMII-to-RGMII and AXI Ethernet Subsystem IP cores. We’ll then test the design on hardware by running an echo server on lwIP. Our target hardware will be the ZedBoard armed with an Ethernet FMC, which adds 4 additional Gigabit Ethernet ports to our platform. Ports 0 to 2 of the Ethernet FMC will connect to separate AXI Ethernet Subsystem IPs which will be configured in DMA mode.
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I just got the news about the new ARTY $99 FPGA evaluation kit being released and I thought it was worth a mention. At the $99 price point and with the Arduino shield connector, they’ll attract a lot of hobbyists who can now hook up one of the many existing Arduino shields to a Series-7 FPGA. Another interesting thing is that it ships with a webserver reference design so you’ve got a head-start on your IoT applications.
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In recent weeks I’ve been working with some great people on an incredible new product for open water swimmers: OnCourse Goggles. Today we announced the launch of a KickStarter campaign which might help us to reach more people with this technology.
Check it out here: https://www.kickstarter.com/projects/oncoursegoggles/oncourse-goggles-navigate-open-water-and-swim-stra
Your support is greatly appreciated!
Here are some photos of the prototype electronics which I assembled in my lab. My soldering iron is in the background, but nothing on this board was actually hand soldered, it’s all QFNs, LGAs and 0402 passives.
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