Using SVN with HDL designs

 Posted on June 29, 2011  |  Jeff Johnson

Most companies involved in code design manage their sources using SVN. If you’re not doing it, you should be. There are a multitude of websites explaining the benefits of using SVN so I wont go there. This post is about the best way to use SVN for HDL designs. HDL designs typically involve source files, netlist files and bitstreams. As in software design, the best way to use SVN is to commit source files only. [Read More]

Generating Clock Domain Crossing FIFOs

 Posted on September 23, 2009  |  Jeff Johnson

Tutorial Overview In some FPGA designs, it is necessary to interface two devices that operate in different clock domains. One solution to crossing from one clock domain to another is by using FIFOs with independent read and write clocks. In this tutorial, we will generate FIFOs with independent read and write clocks, and non-symmetric aspect ratios. This tutorial was written for the Aurora to Ethernet Bridge project in which we want to interface the Ethernet MAC to the Aurora core. [Read More]
aurora 

Tri-mode Ethernet MAC

 Posted on October 20, 2008  |  Jeff Johnson

Tutorial Overview The Virtex-5 Embedded Tri-mode Ethernet MAC is useful for designs requiring Ethernet connectivity. Fortunately, Xilinx has made it easy for us to start developing with the Ethernet MACs by providing several online examples and application notes. One of the examples can be obtained when you use CORE Generator to generate the Ethernet MAC wrapper. The generated example is a simple design that mirrors incoming Ethernet packets, swapping the source and destination MAC addresses. [Read More]

Basic Coregen Tutorial

 Posted on October 18, 2008  |  Jeff Johnson

Tutorial Overview In this tutorial, we will generate a Multiplier IP core using the Xilinx CORE Generator version 10.1. What will you learn By following this tutorial, you will learn: How to generate an IP core using the CORE Generator What files are generated and how to use them  Requirements Before following this tutorial, you will need to do the following: Buy an ML505/ML506/ML507 or XUPV5 board if you don’t already have one. [Read More]

Generating the Aurora Core

 Posted on October 18, 2008  |  Jeff Johnson

Tutorial Overview In this tutorial, we will generate an Aurora IP core using the Xilinx CORE Generator version 10.1. The Aurora core can be used as a high-speed serial communications link for connecting multiple FPGAs or interfacing to other serial devices. Requirements To generate the Aurora core with CORE Generator, you will first need to register with Xilinx to obtain a license to use the Aurora core. It is a free and simple process that involves accepting a license agreement. [Read More]
aurora 

Generating the Ethernet MAC

 Posted on October 18, 2008  |  Jeff Johnson

Tutorial Overview The Virtex-5 FPGA is particularly useful in Ethernet applications because it contains embedded Tri-mode 10/100/1000 Mbps Ethernet MACs. If you have done Ethernet designs before, you will know that Xilinx’s “soft” Ethernet MAC IP cores are not free and designing one yourself would be quite an undertaking. In this tutorial, we will generate an embedded Tri-mode Ethernet MAC IP wrapper using the Xilinx CORE Generator version 10.1. Requirements [Read More]