ISE

I know I’ve gone through the Base System Builder many times before but I’m writing a few more advanced tutorials for version 14.7 and they all need a starting point. So in this post we will use the handy Base System Builder of the Xilinx Platform Studio (EDK) to put together a simple project for the ZC706 evaluation board.

Requirements

You will need the following :

• Xilinx ISE Design Suite 14.7

Create the Project

Follow these steps to create the project:

In the previous tutorial on using the SDK, we exported our base project from EDK to SDK and then we ran a simple software application that printed “Hello World” in the terminal window. In this tutorial, we will do something more useful than saying hello, instead we will illustrate the concept of communicating with a peripheral from C code running on the Microblaze. More specifically, we will read the DIP switch settings and display them on the terminal screen using printfs. Our C code will poll the switches constantly so that any change will be reflected in the terminal window.

Most companies involved in code design manage their sources using SVN. If you’re not doing it, you should be. There are a multitude of websites explaining the benefits of using SVN so I wont go there. This post is about the best way to use SVN for HDL designs.

HDL designs typically involve source files, netlist files and bitstreams. As in software design, the best way to use SVN is to commit source files only. That means, don’t commit netlist files or bitstream files. Our challenge is to ensure that someone who loads our sources from SVN to a clean slate (let’s call him Jack) will be able to re-generate the netlists and bitstream files without a problem.

What am I learning here?

In this post we’ll look at using the Base System Builder in EDK version 13.1. Specifically you’ll learn:

1. How to create an EDK project with the Base System Builder
2. How to add a software application to an EDK project
3. How to implement and test your design

Requirements

You will need the following :

• One ML505/ML506/ML507 or XUPV5 board (or actually any board supported by Xilinx).
• Xilinx ISE Design Suite 13.1 (including EDK)

Create the Basic Project

Follow these steps to create the basic project: