Ethernet

Tutorial Overview In some FPGA designs, it is necessary to interface two devices that operate in different clock domains. One solution to crossing from one clock domain to another is by using FIFOs with independent read and write clocks. In this tutorial, we will generate FIFOs with independent read and write clocks, and non-symmetric aspect ratios. This tutorial was written for the Aurora to Ethernet Bridge project in which we want to interface the Ethernet MAC to the Aurora core. [Read More]

Tutorial Overview The Virtex-5 Embedded Tri-mode Ethernet MAC is useful for designs requiring Ethernet connectivity. Fortunately, Xilinx has made it easy for us to start developing with the Ethernet MACs by providing several online examples and application notes. One of the examples can be obtained when you use CORE Generator to generate the Ethernet MAC wrapper. The generated example is a simple design that mirrors incoming Ethernet packets, swapping the source and destination MAC addresses. [Read More]

Tutorial Overview The Virtex-5 FPGA is particularly useful in Ethernet applications because it contains embedded Tri-mode 10/100/1000 Mbps Ethernet MACs. If you have done Ethernet designs before, you will know that Xilinx’s “soft” Ethernet MAC IP cores are not free and designing one yourself would be quite an undertaking. In this tutorial, we will generate an embedded Tri-mode Ethernet MAC IP wrapper using the Xilinx CORE Generator version 10.1. Requirements [Read More]