See it live: The demo described in this post will be displayed live at the EBV Elektronik booth at Embedded World 2024 on April 9-11. I’ll be attending too, so get in touch if you’re keen to meet up. Over the last few months I’ve been lucky to work with two very talented people on an interesting project for multi-camera machine vision applications: Gianluca Filippini and Mario Bergeron. Back in 2022, I was contacted by Gianluca, an engineer from EBV Elektronik.
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Update 2020-02-07: Missing Link Electronics has released their NVMe Streamer product for NVMe offload to the FPGA, maximum SSD performance, and they have an example design that works with FPGA Drive FMC!
Probably the most common question that I receive about our SSD-to-FPGA solution is: what are the maximum achievable read/write speeds? A complete answer to this question would require a whole other post, but instead for today I’m going to show you what speeds we can get with a simple but highly flexible setup that doesn’t use any paid IP.
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The Intel Movidius Neural Compute Stick (NCS) is a neural network computation engine in a USB stick form factor. It’s based on the Myriad-2 chip, referred to by Movidius as a VPU or Visual Processing Unit, basically a processor that was specifically designed to accelerate neural network computations, and with relatively low power requirements. The NCS is a great match for single board computers like the Raspberry Pi, the Beagle Bone and especially the PYNQ-Z1.
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See what the PYNQ-Z1 and the PYNQ Computer Vision overlay are capable of doing with a 720p standard HD video stream. In the video we run a 2D filter and dilate function on the incoming video, first using the Python OpenCV functions (ie. without hardware acceleration), then we test it again with the accelerator IPs running on the FPGA. Without acceleration, we get a frame rate of 5 frames per second.
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This video demonstrates how you would typically go about accelerating a Python function or algorithm on the Zynq-7000 with PYNQ. The function I chose to base this video on is the Finite Impulse Response (FIR) filter because the SciPy package contains the lfilter function which can be used for this purpose, and because the Xilinx IP catalog has a free FIR filter IP core. If you instead wanted to implement the accelerator in HLS, the process would be very similar, you would just have to design your accelerator with AXI-Streaming interfaces and ensure that the TLAST signals were properly managed.
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In this video tutorial we create a custom PYNQ overlay for the PYNQ-Z1 board. Probably the simplest PYNQ overlay possible, it contains one custom IP (an adder) with an AXI-Lite interface and three registers accessible over that interface: a, b and c. To use the IP we write a number to input registers a and b, and then we read the output register c which contains the sum of a and b.
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I’ve been totally overloaded with projects in the last couple months but I’m back with some really exciting news today. A few months back a company called IntelliProp, based in Colorado, released a NVMe Host Accelerator IP core for interfacing FPGAs with NVMe SSDs. This IP core allows reads and writes to be performed directly from the FPGA fabric, without the latency overhead of an operating system (read about the NVMe speed tests I did under PetaLinux).
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Rick Merritt wrote an interesting article on EETimes titled Red Hat Drives FPGAs, ARM Servers. It seems that Red Hat and the major FPGA vendors are going to get together in March to work out a standard software interface for FPGA accelerator boards. The success of high-level synthesis tools in recent years has re-ignited interest in FPGA-based hardware accelerators, as development times on FPGA hardware has seen massive reductions thanks to OpenCL and Vivado HLS, among others.
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One of my most common customer requests is to speed up execution of a software application using FPGA hardware acceleration. If the application runs on a PC or server, you can achieve impressive performance gains by using off-the-shelf FPGA development boards for PCI Express.
Here is a comparison of the available 7 Series FPGA boards for PCI Express applications:
AC701 Artix-7 KC705 Kintex-7 VC707 Virtex-7 VC709 Virtex-7 $1295 $1695 $3495 $4995 XC7A200T-2FBG676C XC7K325T-2FFG900C XC7VX485T-2FFG1761 XC7VX690T-2FFG1761C 4-lane Gen2 PCIe 8-lane Gen2 PCIe 8-lane Gen2 PCIe 8-lane Gen3 PCIe 1GB DDR3 SODIMM 1GB DDR3 SODIMM 1GB DDR3 SODIMM 4GB DDR3 SODIMM x2 8Kb EEPROM 8Kb EEPROM 8Kb EEPROM 1KB EEPROM No BPI Flash 128MB BPI Flash 128MB BPI Flash 32MB BPI Flash 32MB Quad SPI 16MB Quad SPI 16MB Quad SPI No Quad SPI Flash SD Card slot SD Card slot SD Card slot No SD No LPC FMC 1x LPC FMC No LPC FMC No LPC FMC 1x HPC FMC (*) 1x HPC FMC (*) 2 x HPC FMC 1x HPC FMC (*) 1x SFP 1x SFP+ 1x SFP+ 4x SFP/SFP+ 1GB Ethernet 1GB Ethernet 1Gb Ethernet No Ethernet No USB No USB No USB No USB UART over USB UART over USB UART over USB UART over USB HDMI out HDMI out HDMI out No Video XADC header XADC header AMS port No Analog (*) Note: These HPC FMC connectors are only partially populated which means that they wont be able to support all standard FMCs.
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