Rambling

Since their invention, FPGAs have been burdened by a problem that has held them back from more widespread adoption: they’re too hard to program. Xilinx knows this, which is why they spent hundreds of millions of dollars developing the Vivado Design Suite and more importantly Vivado HLS (high-level synthesis) which enables high-performance hardware designs to be programmed in C/C++. Well a new company called QuickPlay has created their own solution to this problem. [Read More]

In recent weeks I’ve been working with some great people on an incredible new product for open water swimmers: OnCourse Goggles. Today we announced the launch of a KickStarter campaign which might help us to reach more people with this technology. Check it out here: https://www.kickstarter.com/projects/oncoursegoggles/oncourse-goggles-navigate-open-water-and-swim-stra Your support is greatly appreciated! Here are some photos of the prototype electronics which I assembled in my lab. My soldering iron is in the background, but nothing on this board was actually hand soldered, it’s all QFNs, LGAs and 0402 passives. [Read More]

I ran into a problem on the JTAG boundary scan and after hours of googling and probing with my oscilloscope, I finally came across a solution. Firstly I should say that if you are having a JTAG problem with this board, make sure that your DIP switch settings are right. There are two DIP switches (SW11 and SW4) that should be set correctly for your particular JTAG setup. If you are using a USB cable plugged into the slot labelled “JTAG” on the faceplate of the ZC706, you should use the settings 00000 for SW11 and 01 for SW4. [Read More]

Here is a recent presentation I made on outsourcing FPGA design work.

Outsourcing FPGA Design: Pros and cons

View more presentations from jeffjohnsonau.

You might already know I’m interested in the application of FPGAs in the financial markets, a field that has been growing over the last few years. JP Morgan has been working on this over the last 3 years and its paying off. JP Morgan supercomputer offers risk analysis in near real-time Prior to the implementation, JP Morgan would take eight hours to do a complete risk run, and an hour to run a present value, on its entire book. [Read More]

Recently I was asked this question by a reader: “Is it possible to make a design large enough to make the FPGA melt?”. I don’t know why you would want to melt an FPGA, but the idea is interesting so its worth writing about. I’ve actually had people tell me rumors that if you made a design that utilized 90-100% of the resources in an FPGA that it would melt itself. [Read More]