Tcl-VHDL-Verilog

Tcl automation is one of the most powerful features integrated into the Vivado and Xilinx SDK tools and should be fully exploited to maximize your productivity as an FPGA developer. In this post I’ve put together a “cheat sheet” of some of the most useful commands and tricks that you can use to get more done through Tcl scripting. If you want more things added to the list, please let me know in the comments section at the end. [Read More]

Let’s say we want to be able to switch dynamically between two (or more) clocks. In the Virtex FPGAs we have a primitive which allows us to do just this, it’s called the BUFGCTRL. The BUFGCTRL is a global clock buffer (like BUFG) which has two clock inputs and a series of control inputs that allow you to select between the two clocks. The great thing about the BUFGCTRL is that it allows you to switch between clocks “glitch free”. [Read More]

This is the first part of a series of posts I will write on various code structures and examples for HDL designs. Here I want to talk about the generate statement and particularly the for loop. Most programmers think of a for loop as being a code segment that is repeated during execution of the program. The generate for loop is similar in concept however the difference is that the code segment is repeated on compilation time. [Read More]

In a previous post I wrote about using SVN with HDL designs and how to do it most effectively. Here I want to write about having your peripheral cores automatically generate the netlists they use when the project is compiled, for example when you build the bitstream of an XPS project. Firstly I’ll give you an example where it would be useful. Let’s say I have a peripheral that contains a FIFO. [Read More]

Why can’t I find my signals in Chipscope inserter? Often you want to assign a constraint to a particular signal in your design, or you want be able to find a particular signal in Chipscope inserter. In both cases, the signal must be in the physical design database (ie. in the .NCD file - Native Circuit Description) which is generated by the mapper. Not all signal names in your HDL code will end up in the NCD, some of them will be absorbed into logic blocks and grouped into a different signal name. [Read More]